1. Technical Field
The present invention relates to evaluating the performance of data processing systems. More specifically, the present invention relates to the design of high-performance processing chips.
2. Description of Related Art
Timing closure in designing high-performance Very Large Scale Integration (VLSI) chips in current and next generation process technologies is a complex task. It entails carefully iterating between logic design (through choosing correct power levels for circuits and buffering long wires), physical design (placement and routing), layout extraction (to compute interconnect delays and circuit loadings) and timing analysis (to compute path delays and identify cycle-time limiting paths). Timing analysis actually permeates throughout this iteration.
A crucial step in timing analysis is evaluating the effect of interconnect wiring on path delays, because interconnect effects can comprise as much as 70% of the path delay. Before full layout is available, the interconnect is usually estimated by constructing Steiner routes (which ignore blockages from circuits and other nets) to each segment of the estimated network. After full layout, this same information is obtained from extraction of resistance and capacitance values from interconnect geometries.
The inaccuracy of the Steiner tree networks and the default electrical characteristics leads to expensive design iterations. Typically, after a first full physical design is obtained, the timing analysis with extracted data will report numerous failures (paths violating cycle-time). To correct these failures, a new logic design is performed (i.e. logic repartitioned, buffers added), and timing analysis is performed with the previously extracted interconnect data to account for interconnect effects. However, by the time this logic design is completed, the interconnect data is obsolete. This results from the fact that the logic changes require a new physical design which might change the interconnect significantly. Hence, a new physical design and extraction is required. This leads to serious loss of productivity. The new physical design requires completely legalizing the placement, obtaining a routing with minimum overflows, and a full layout extraction. This activity can take days for a large design.
Therefore, it would be desirable to have a method to achieve chip design closure in a timely manner by reducing the number of costly iterations of full-chip routing, extraction, and timing and noise analysis.
The present invention provides a method for timing and noise analysis in designing data processing chips. The process begins by wiring all unconnected nets in the design and then using a 2xc2xd D capacitance extraction technique built into a detailed router to extract all of the wired nets. The data from the extracted nets is then processed using a timing and analysis tool. Optimization programs are then used to generate fixes for any nets in the design which contribute to timing and noise failures.
The present invention gives designers the capability of fast and accurate interconnect extraction within the routing tool. In addition, this technique is incremental. Any wiring changes can be quickly re-extracted, since only local information is required for extraction. This incremental capability allows designers to perform quick iterations of wiring, extraction and timing analysis.